Memory Map
(For historical context, see the original Kestrel 2 memory map.)
| Low | High | Size | Purpose |
|---|---|---|---|
000000 |
003FFF |
16KiB | ROM |
004000 |
007FFF |
16KiB | unmapped1 |
008000 |
00FFFF |
32KiB | unmapped2 |
010000 |
01BFFF |
48KiB | IPL/Video RAM |
01C000 |
01FFFF |
16KiB | unmapped3 |
020000 |
020003 |
4B | GPIA |
020004 |
02FFFF |
64KiB | unmapped2 |
030000 |
030003 |
4B | KIA |
030004 |
FFFFFF |
~16MiB | unmapped2 |
Addresses not explicitly listed above either aren't assigned or are mirrors of previous address decode domains.
IPL Resources
The ROM has sufficient space to hold around 12KiB worth of executable code, considering 4KiB for font and keyboard tables. Thus, the ROM image can hold about 3000 CPU instructions. This is big enough to hold the console output code, keyboard input code, some basic SD card access routines, and a minimal, interactive bootstrap program called "TIM/V".
The IPL RAM is FPGA-internal block RAM, always available for use by the ROM image. It also doubles as the source of video data for the MGIA core. All together, the IPL RAM can provide up to three 16KB pages of video, which you can select with some bits set in the GPIA output register. If required, the last 384 bytes of video RAM may also be used for data storage without affecting the displayed image. At cold-boot, $10000-$13E80 is selected as the default video page.
Expansion Memory
Plenty of expansion space exists to explore interfacing with external memory or other peripherals yet to be added or designed. Using this space will entail modifying the Verilog source code to suit your needs. The CPU provides a true 64-bit address bus, even though the Kestrel-2DX as currently implemented does not use all address bits available. It is entirely possible your programs will be made to run on an arbitrarily expanded Kestrel-2DX. For this reason, your programs must never depend upon behavior of any unmapped memory regions.
I/O Space
The I/O space contains memory-mapped I/O resources familiar to Kestrel 2 programmers: the GPIA, KIA, etc. Additional cores may appear in the future.
1 Writes ignored; reads always returns $CC. You should not depend on this behavior.
2 Contains mirrors of the previous block of address space. You should not depend on this behavior.
3 Loads or stores to this region of address space will not generate a memory transaction acknowledgement, causing the CPU to halt indefinitely. Only a hard reset will restore operation. This is a known bug, and will be fixed in a future revision of the design.